This invention relates generally to metal-insulator-semiconductor (MIS) devices and production methods and more particularly to a self-aligned method of fabricating MIS semiconductor devices having lightly doped-drain (LDD) structures and inverse-T gate structures.
As the microminiaturization of metal-oxide-semiconductor (MOS) transistors progresses, two different effects become a problem due to the short-channel limitations, these are the punch-through and hot-carrier injection effects. For a bipolar transistor with a very narrow base width or a base with relatively low doping, a breakdown may be caused by the punch-through effect, in which the neutral base width is reduced to zero at a sufficient V.sub.cb and the collector depletion region is in direct contact with the emitter depletion region. In a MOS transistor, a concentration of the electric field at the end of the drain causes hot carriers to be captured mainly at the interface between the substrate and the insulator film or in the insulator film. The operating characteristics of such MOS transistors can drift, due to an accumulation of the electric charge.
FIG. 1 illustrates a prior art attempt in an LDD structure 10 to prevent the above concentration of an electric field at the end of the drain. Structure 10 has a pair of lower-carrier concentration areas 12 and 14 on a gate electrode 16 side of a source area 18 and a drain area 20, and are formed on the surface of a p-type silicon substrate 22 on either side of gate electrode 16. In fabricating structure 10, LOCOS isolation is used to produce self-aligned implants to a field oxide. (See, Rabbat, G., Handbook of Advanced Semiconductor Technology and Computer Systems, (Van Nostrand Reinhold Co.: New York) 1988, pp. 233-235 [LOCOS isolation process steps].) The LOCOS isolation produces an oxide film 24 formed on substrate 22 that surrounds a self-aligned active transistor area. Over this active area is deposited a gate oxide film 26. Polysilicon is then deposited on top of this to form gate electrode 16. Low-concentration areas 12 and 14 are formed by introducing phosphorous to the surface of silicon substrate 22 by ion implantation, and by using gate electrode 16 as a mask. An oxide film is then deposited over both gate electrode 16 and gate insulator film 26. The oxide film is etched afterwards, leaving a sidewall insulator film 28. Source area 18 and drain area 20 are formed by a self-aligned ion implantation of arsenic, using gate electrode 16 and sidewall insulator film 28 as a mask. An oxide film 30, a source electrode 32, and a drain electrode 34 complete the fabrication of structure 10. Low-concentration areas 12 and 14 suppress widening of the depletion layer and prevent punch-through between source area 18 and drain area 20, they also reduce electric field concentration at end of the drain and thereby suppresses deterioration of MOS transistor characteristics due to hot carrier injection phenomenon.
In recent years, however, demand for greater integration of semiconductor devices has brought about a need for further microminiaturization of MOS transistors. In very small MOS transistors with LDD structures, an electric field accumulates at the ends of their drains and an injection of an electric charge into sidewall insulator film 28 occurs. As was happening in normal MOS transistors, a depletion layer forms around low-concentration areas 12 and 14. This increases the resistance of areas 12 and 14, and that reduces the current carrying capacity of the transistor.
To solve this problem, a method evolved that extends gate electrode 16 to the areas above the low-concentration areas 12 and 14. Thus creating an inverted-T gate structure. An electric field from the gate potential is impressed on the surface of low-concentration areas 12 and 14, such that the electric field strength is weakened in the planar direction. The injection of hot carriers is thereby suppressed.
However, since etching is used to form the inverted-T gate, it is difficult to control the thickness of the thinner parts of the inverted-T. It is also difficult to set the carrier density or the depth of the low-concentration areas 12 and 14, because areas 12 and 14 are formed through these thinnest parts. This results in wide production deviations in the characteristics of the MOS transistor yield.
In the present invention, the inverted-T gate structure is formed after the formation of low-concentration areas, so the impurity concentration or depth of low-concentration areas can be easily controlled and variation in characteristics between production units reduced. Even if the low-concentration areas are formed after temporarily forming a titanium layer or nitride layer, the thickness of titanium layer formed by sputtering can be set precisely, so impurity concentration and depth of low-concentration areas can be obtained with some degree of accuracy.
In the inverted-T polysilicon gates of prior art, time control of amount of etching and precise process control of the formation of a natural oxide layer were required. But these became extremely difficult as microminiaturization of the devices progressed. Deviations in element characteristics and decreased yield resulted. In contrast, a process of the present invention is capable of forming an inverted-T gate structure extremely simply and accurately by forming a titanium layer. It can also accurately build an inverse T-structure without being greatly affected by microminiaturization.
The present invention solves the above problems, and yields a small MOS transistor having a practical production method that suppresses punch-through and hot carrier injection without degrading the operating characteristics.